Main memories of computer systems are generally formed using dynamic semiconductor memory chips (DRAM). For this purpose, a number of memory chips are combined on a small circuit board, a memory module. Such a memory module is often also referred to as a DIMM or SIMM memory. At least a portion of such memory modules then forms the main memory. The data traffic between the main memory and the processor device of the computer system is handled by means of a control device. The latter is arranged between one data bus, which connects it to the processor device, and a further data bus, which connects it to the main memory. In many computer systems, particularly relatively simple computer systems, both buses have the same data width. In this case, the number of memory chips to be selected for a data transfer operation is chosen such that their total number of data inputs and outputs is equal to the data width of the buses. By way of example, in the case of a simple desktop computer for so-called home use, the data width of the buses is nowadays usually equal to 64. If memory chips of so-called “.times.8” organization are used with a 64 bit wide data bus as main memory, 8 memory chips are provided for a single data transfer operation, since 8 memory chips having a data width of 8 bits per chip produce precisely 64 bits.
In the case of high-quality computer systems, such as network servers or workstations, the requirements made in respect of the memory chips being free of errors are often more stringent than in the case of the relatively simple computer systems described above. For this reason, such computer systems have so-called error correction devices which, upon storage of data in the main memory, generate one or more error correction bits (ECC bits or ECC information) per data record and transfer this information so that it is stored together with the data to be stored in the main memory. Correspondingly, when data stored in the main memory are read out, the associated ECC information is also concomitantly read out and transferred to the error correction device for corresponding evaluation and, insofar as is necessary and possible, error recovery (reconstruction of the original data). In this case, it is even possible to eliminate errors (in the sense of data reconstruction) which relate to the entire data width of one of the memory chips (so-called “chipkill”). The error correction device is generally part of the abovementioned control device.
Since this error detection and correction procedure is carried out chip by chip, two alternatives emerge for populating a memory module with memory chips: 1) either memory chips having a data width of 9 bits are used instead of memory chips having a data width of e.g. 8 bits (so-called .times.8 organization) (other examples: memory chips having .times.5 organization (=data width of 5 bits) instead of memory chips of .times.4 organization) or 2) use is made of customary memory chips (e.g. .times.8 or .times.4 organization) for storing the data and, additional memory chips having a data width which in total, i.e. including additional memory chips, have a combined data width that corresponds to the number of memory chips used for data storage.
However, the following disadvantages accrue to the above-mentioned alternatives: in the case of alternative 1, it is necessary for a developer and manufacturer of memory chips to develop and manufacture two different chip variants for the same nominal storage capacity, namely, e.g., chips of .times.8 organization and chips of .times.9 organization. Correspondingly, a developer and manufacturer of the matching memory modules also has to develop and manufacture two circuit boards which are different from one another and are adapted to the respective memory chips.
In the case of the second alternative, although the developer and manufacturer of memory chips can restrict itself to a single type of memory chip (e.g. to those having a .times.8 organization), the developer and manufacturer of the memory modules nevertheless has to develop two different variants, namely a first variant, in which only memory chips for storing the memory data are used for placement, and a second variant involving additional placement also of at least one memory chip for storing the error correction data. In accordance with the two variants, different line routings are needed on the different memory modules, since the line routing has to be optimized separately for each variant in order to avoid losses in the signal quality.
It is thus apparent that a need exists to improve operation of memory chips and still provide for error correction.